CPU: Control Unit, ALU & the Fetch-Decode-Execute Cycle
What it is
The CPU (Central Processing Unit) is the computer's "brain" — it has two main working parts, the Control Unit (CU) and the Arithmetic Logic Unit (ALU), plus a small set of high-speed registers that hold data the CPU is actively using.
The core method
Every instruction the CPU runs goes through the same three-step cycle, over and over — FETCH (the CU retrieves the next instruction from memory, using the Program Counter register to know its address), DECODE (the CU figures out what operation the instruction means), and EXECUTE (the ALU actually performs the arithmetic or logical operation, or the CU carries out a non-arithmetic action like a jump). The Program Counter is incremented during the fetch itself, as soon as its address has been handed to memory, so it already points at the next instruction by the time execute runs; the cycle then repeats. The CU never calculates anything itself — it only directs traffic; all real computation happens in the ALU.
Worked example
An instruction "ADD R1, R2" sits at memory address 200, and the Program Counter currently holds 200. Fetch: the CU reads the instruction at address 200 into the Instruction Register, and the Program Counter is incremented to 201 as part of that same fetch. Decode: the CU recognises this as an addition instruction involving registers R1 and R2. Execute: the ALU adds the values in R1 and R2 and stores the sum in R1. The Program Counter already holds 201, so the CU fetches the next instruction from address 201 on the following cycle — and had this been a jump, execute would have overwritten the PC rather than merely skipping an increment.
Common traps
- Thinking the Control Unit performs calculations itself — it only fetches, decodes, and coordinates; the ALU does all arithmetic and logic.
- Confusing the Program Counter (holds the address of the next instruction) with the Instruction Register (holds the actual contents of the instruction currently being executed).
- Assuming a higher clock speed alone guarantees better performance — clock speed only measures how many cycles happen per second, not how much useful work each cycle does, which also depends on cache, cores, and instruction efficiency.
What the exam tests here
Across the 3 papers we hold, this skill was asked 3 times, around 1 a paper.
What it actually asked:
- CPU unit responsible for fetch-decode-execute (2026)
- identify the operation the ALU does not perform (2026)
- performance metric for high-precision floating-point work (2026)
Worked example 2 — one full machine cycle
Describe what happens, register by register, when the CPU executes a single instruction.
Fetch. The program counter (PC) holds the address of the next instruction. That address is copied to the memory address register (MAR), the memory returns the instruction into the memory buffer register (MBR), and it is copied into the instruction register (IR). The PC is then incremented — and it is incremented during fetch, not after execution, which is why a jump instruction has to overwrite the PC rather than merely skip an increment.
Decode. The control unit reads the opcode in the IR and works out which operation is required and where its operands are.
Execute. The ALU performs the operation; the accumulator or a general-purpose register receives the result, and status flags — zero, carry, sign, overflow — are set as a side effect.
Store. If the instruction requires it, the result is written back to memory.
The cycle then repeats. Everything a processor does is this loop; "speed" is how many of these loops complete per second and how much work each one carries.
Speed technique
Memorise the register roles: PC — address of next instruction. IR — instruction being executed. MAR — address being accessed. MBR/MDR — data in transit. Accumulator — arithmetic result. Flags — outcome bits.
Clock speed alone does not determine performance: instructions per cycle, pipeline depth and cache hit rate all matter, which is why a 2 GHz processor can outperform a 3 GHz one.
A pipeline overlaps the stages of consecutive instructions, so a k-stage pipeline can approach k× throughput without any increase in clock speed.
Terms you must not confuse
- Clock speed vs performance — cycles per second, not work per second.
- Core vs processor — a multi-core processor is one chip with several complete execution units.
- RISC vs CISC — few simple fixed-length instructions versus many complex variable-length ones.
Check yourself
- Which register holds the address of the next instruction?
Show answer
PC. - When is the PC incremented?
Show answer
During fetch. - What sets the zero flag?
Show answer
The ALU, as a side effect of an operation.
Try it: CPU questions
Real questions from the PGCET MBA bank on exactly this skill. Pick an answer to see the full solution — the intuition, the worked steps, the faster methods and the traps.
What does the acronym 'CPU' stand for?
Show the answer and worked solution
Answer: option C
CPU stands for Central Processing Unit — the component of a computer that carries out the instructions of a program by performing arithmetic, logic, control, and input/output operations.
'Computer Processing Unit', 'Central Program Unit', and 'Central Processor Utility' are all invented near-misses that swap in a plausible-sounding but incorrect word.
So the acronym CPU stands for Central Processing Unit, option C.
What is the primary function of the Control Unit (CU) inside the CPU?
Show the answer and worked solution
Answer: option A
The Control Unit acts as the CPU's coordinator: it fetches and interprets instructions and generates the control/timing signals that direct the ALU, registers, memory, and I/O devices — but it does not perform the arithmetic/logic calculations itself.
Option B describes the ALU, option C describes secondary (non-volatile) storage, and option D describes the output unit.
So the Control Unit's primary function is to direct and coordinate the CPU's other units by generating timing and control signals, option A.
Which CPU register holds the memory address of the NEXT instruction to be fetched and executed?
Show the answer and worked solution
Answer: option A
The Program Counter (PC) keeps track of the address of the next instruction to be fetched from memory, and is automatically updated so the CPU always knows where to fetch from next.
The Accumulator holds intermediate arithmetic results (not addresses), the Instruction Register holds the actual instruction that has ALREADY been fetched (not an address to fetch next), and the Memory Data Register holds the data being transferred to/from memory rather than the address of the next instruction.
So the register holding the address of the next instruction to fetch is the Program Counter (PC), option A.
Which CPU register holds the address of the memory location that is currently being read from or written to?
Show the answer and worked solution
Answer: option B
The Memory Address Register (MAR) holds the address of the specific memory location that the CPU is currently accessing, for either a read or a write operation.
The Memory Data Register holds the actual data value being transferred, not the address.
The Instruction Register holds the content of an already-fetched instruction, and the Program Counter holds only the address of the NEXT instruction to fetch, which is a narrower, specific case rather than a general memory-access address register.
So the register holding the address of the memory location currently being accessed is the Memory Address Register (MAR), option B.
Which CPU register holds the actual piece of data being transferred to or from memory during a read or write operation (also known as the Memory Buffer Register)?
Show the answer and worked solution
Answer: option D
The Memory Data Register (MDR), sometimes called the Memory Buffer Register (MBR), holds the actual data value being moved between the CPU and memory during a read or write — not the address of that data.
The Memory Address Register holds only the address (not the data itself), the Program Counter holds the address of the next instruction, and the Instruction Register holds the content of a fetched instruction rather than data being transferred to/from memory.
So the register holding the actual data transferred to or from memory is the Memory Data Register (MDR), option D.
Answer above — every one shows its working.